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general description the max4691?ax4694 are low-voltage cmos analog ics configured as an 8-channel multiplexer (max4691), two 4-channel multiplexers (max4692), three single- pole/double-throw (spdt) switches (max4693), and four spdt switches (max4694). the max4691/max4692/max4693 operate from either a single +2v to +11v power supply or dual ?v to ?.5v power supplies. when operating from ?v sup- plies they offer 25 on-resistance (r on ), 3.5 (max) r on flatness, and 3 (max) matching between chan- nels. the max4694 operates from a single +2v to +11v supply. each switch has rail-to-rail signal handling and a low 1na leakage current. all digital inputs are 1.8v logic-compatible when oper- ating from a +3v supply and ttl compatible when operating from a +5v supply. the max4691?ax4694 are available in 16-pin, 4mm ? 4mm qfn and tqfn and 16-bump ucsp pack- ages. the chip-scale package (ucsp) occupies a 2mm ? 2mm area, significantly reducing the required pc board area. applications audio and video signal routing cellular phones battery-operated equipment communications circuits modems features ? 16 bump, 0.5mm-pitch ucsp (2mm x 2mm) ? 1.8v logic compatibility ? guaranteed on-resistance 70 (max) with +2.7v supply 35 (max) with +5v supply 25 (max) with ?.5v dual supplies ? guaranteed match between channels 5 (max) with +2.7v supply 3 (max) with ?.5v dual supplies ? guaranteed flatness over signal range 3.5 (max) with ?.5v dual supplies ? low leakage currents over temperature 20na (max) at +85? ? fast 90ns transition time ? guaranteed break-before-make ? single-supply operation from +2v to +11v ? dual-supply operation from ?v to ?.5v (max4691/max4692/max4693) ? v+ to v- signal handling ? low crosstalk: -90db (100khz) ? high off-isolation: -88db (100khz) max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package ________________________________________________________________ maxim integrated products 1 functional diagrams 19-1945; rev 4; 8/08 pin configurations appear at end of data sheet. functional diagrams continued at end of data sheet. ucsp is a trademark of maxim integrated products, inc. part temp range pin-package max4691 ebe-t -40 c to +85 c 16-bump ucsp* max4691ege -40 c to +85 c 16 qfn-ep ? max4691ete+t -40 c to +85 c 16 tqfn-ep ? max4692 ebe-t -40 c to +85 c 16-bump ucsp* max4692ege -40 c to +85 c 16 qfn-ep ? max4692ete+t -40 c to +85 c 16 tqfn-ep ? max4693 ebe-t -40 c to +85 c 16-bump ucsp* max4693ege -40 c to +85 c 16 qfn-ep ? max4693ete+t -40 c to +85 c 16 tqfn-ep ? max4694 ebe-t -40 c to +85 c 16-bump ucsp* max4694ege -40 c to +85 c 16 qfn-ep ? max4694ete+t -40 c to +85 c 16 tqfn-ep ? ordering information *requires special solder temperature profile described in the absolute maximum ratings section. ucsp reliability is integrally linked to the user? assembly methods, circuit board, and envi- ronment. see the ucsp reliability notice in the ucsp reliability section for information. ? ep = exposed pad. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. max4691 x0 x1 x2 x3 x4 x5 x6 x7 logic c b a en x for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ingle +3v supply (v+ = +2.7v to +3.6v, v- = 0, v ih = +1.4v, v il = +0.4v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 3, 4, 5) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +12v v+ to v- (max4691/max4692/max4693) ..............-0.3v to +12v voltage into any terminal (note 1) ...... (v- - 0.3v) to (v+ + 0.3v) continuous current into any terminal ............................. ?0ma peak current w_, x_, y_, z_ (pulsed at 1ms, 10% duty cycle)...........................................................?0ma esd per method 3015.7.......................................................>2kv continuous power dissipation (t a = +70?) 16-bump ucsp (derate 8.3mw/? above +70?) .... 659mw 16-pin qfn (derate 18.5mw/? above +70?) ....... 1481mw 16-pin tqfn (derate 16.9mw/? above +70?) ..... 1349mw operating temperature range .......................... -40? to +85? storage temperature range ............................ -65? to +150? lead temperature (soldering) 16-bump ucsp (note 2) infrared (15s) ..................... +220? vapor phase (60s)..................................................... +215? 16-pin qfn................................................................. +300? 16-pin tqfn............................................................... +300? note 1: voltages exceeding v+ or v- on any signal terminal are clamped by internal diodes. limit forward-diode current to maxi- mum current rating. note 2: this device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board level solder attach and rework. this limit permits only the use of the solder profiles recom- mended in the industry standard specification, jedec 020a, paragraph 7.6, table 3 for ir/vpr and convection reflow. preheating is required. hand or wave soldering is not allowed. parameter symbol conditions t a min typ max units analog switch analog signal range v w , v x , v y , v z , v w _, v x _, v y _, v z _ - 40c to + 85c 0v+v + 25c 45 70 on-resistance (note 6) r on v+ = 2.7v; i w , i x , i y , i z = 1ma v w _, v x _, v y _, v z _ = 1.5v - 40c to + 85c 80 + 25c 2 5 on-resistance match between channels (notes 6, 7) r on v+ = 2.7v; i w , i x , i y , i z = 1ma v w _, v x _, v y _, v z _ = 1.5v - 40c to + 85c 6 + 25c -1 1 w_, x_, y_, z_ off- leakage current (note 9) i w _, i x _, i y _, i z _ v+ = 3.6v; v w , v x , v y , v z = 3v, 0.6v; v w _, v x _, v y _, v z _ = 0.6v, 3v - 40c to + 85c -10 10 na + 25c -2 2 w, x, y, z off-leakage current (note 9) i w(off) , i x(off) , i y(off) , i z ( off ) v+ = 3.6v; v w , v x , v y , v z = 3v, 0.6v; v w _, v x _, v y _, v z _ = 0.6v, 3v - 40c to + 85c -20 20 na + 25c -2 2 w, x, y, z on-leakage current (note 9) i w(on) , i x(on) , i y(on) , i z ( on ) v+ = 3.6v; v w , v x , v y , v z = 0.6v, 3v; v w _, v x _, v y _, v z _ = 0.6v, 3v, or unconnected - 40c to + 85c -20 20 na
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package _______________________________________________________________________________________ 3 electrical characteristics?ingle +3v supply (continued) (v+ = +2.7v to +3.6v, v- = 0, v ih = +1.4v, v il = +0.4v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 3, 4, 5) parameter symbol conditions t a min typ max units input off-capacitance c w _ ( off ) , c x _ ( off ) , c y _ ( off ) , c z _ ( off ) f = 1mhz, figure 7 + 25c 9 pf max4691 68 max4692 36 output off-capacitance c x ( off ) , c y ( off ) , c z ( off ) f = 1mhz, figure 7 max4693 + 25c 20 pf max4691 78 max4692 46 on-capacitance c w ( on ) , c x ( on ) , c y ( on ) , c z ( on ) f = 1mhz, figure 7 max4693 + 25c 30 pf dynamic + 25c 180 300 enable turn-on time ( m ax 4691/m ax 4692/ m ax 4693) t on v w _, v x _, v y _, v z _ = 1.5v; r l = 300 ,c l = 35pf, figure 2 - 40c to + 85c 350 ns + 25c 70 100 enable turn-off time ( m ax 4691/m ax 4692/ m ax 4693) t off v w _, v x _, v y _, v z _ = 1.5v; r l = 300 ,c l = 35pf, figure 2 - 40c to + 85c 120 ns + 25c 200 350 address transition time t trans v w _, v x _, v y _, v z _ = 0, 1.5v; r l = 300 , c l = 35pf, figure 3 - 40c to + 85c 400 ns + 25c 2 90 break-before-make t bbm v w _, v x _, v y _, v z _ = 1.5v; r l = 300 , c l = 35pf, figure 4 - 40c to + 85c 2 ns charge injection q v ge n = 0; r ge n = 0; c l = 1nf, fi g ur e 5 + 25c 0.1 pc off-isolation (note 10) v iso f = 0.1mhz, r l = 50 , c l = 5pf, figure 6 + 25c -70 db crosstalk (note 11) v ct f = 0.1mhz, r l = 50 , c l = 5pf, figure 6 + 25c -75 db digital i/o input logic high v ih 1.4 v input logic low v il 0.4 v input leakage current i in v a , v b , v c , v en = 0 or v+ -1 +1 ? supply + 25c 0.1 positive supply current i+ v+ = 3.6v, v a , v b , v c , v en = 0 or v+ - 40c to + 85c 1 ?
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 4 _______________________________________________________________________________________ electrical characteristics?ingle +5v supply (v+ = +4.5v to +5.5v, v- = 0, v ih = +2v, v il = +0.8v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 3, 4, 5) parameter symbol conditions t a min typ max units analog switch analog signal range v w , v x , v y , v z , v w _, v x _, v y _, v z _ _ - 40c to + 85c 0v+v + 25c 25 35 on-resistance (note 6) r on v+ = 4.5v; i w , i x , i y , i z = 1ma; v w _, v x _, v y _, v z _ = 3.5v - 40c to + 85c 40 + 25c 2 4 on-resistance match between channels (notes 6, 7) r on v+ = 4.5v; i w , i x , i y , i z = 1ma; v w _, v x _, v y _, v z _ = 3.5v - 40c to + 85c 5 + 25c 2 6 on-resistance flatness (note 8) r flat ( on ) v+ = 4.5v; i w , i x , i y , i z = 1ma; v w _, v x _, v y _, v z _ = 1v, 2.25v, 3.5v - 40c to + 85c 8 + 25c -1 1 w_, x_ , y_, z_ off-leakage current (note 9) i w_ , i x _ , i y _ , i z _ v+ = 5.5v; v w , v x , v y , v z = 4.5v, 1v_; v w _, v x _, v y _, v z _ = 1v, 4.5v - 40c to + 85c -10 10 na + 25c -2 2 w, x, y, z off-leakage current (note 9) i w(off) , i x (off) , i y(off) , i z(off) v+ = 5.5v; v w , v x , v y , v z = 4.5v, 1v_; v w _, v x _, v y _, v z _ = 1v, 4.5v - 40c to + 85c -20 20 na + 25c -2 2 w, x, y, z on-leakage current (note 9) i w(on) , i x(on) , i y(on) , i z(on) v + = 5.5v ; v w , v x , v y , v z = 1v , 4.5v _; v w _, v x _, v y _, v z _ = 1v, 4.5v , or unconnected - 40c to + 85c -20 20 na dynamic + 25c 90 130 enable turn-on time ( m ax 4691/m ax 4692/m ax 4693) t on v w _, v x _, v y _, v z _ = 3v; r l = 300 , c l = 35pf, figure 2 - 40c to + 85c 150 ns + 25c 45 60 enable turn-off time ( m ax 4691/m ax 4692/m ax 4693) t off v w _, v x _, v y _, v z _ = 3v; r l = 300 , c l = 35pf, figure 2 - 40c to + 85c 70 ns + 25c 100 140 ad d r ess tr ansi ti on ti m et trans v w _, v x _, v y _, v z _ = 0, 3v; r l = 300 , c l = 35pf, figure 3 - 40c to + 85c 160 ns + 25c 2 35 break-before-make t bbm v w _, v x _, v y _, v z _ = 3v; r l = 300 , c l = 35pf, figure 4 - 40c to + 85c 2 ns charge injection q v gen = 0; r gen = 0; c l = 1nf, figure 5 + 25c 0.2 pc
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package _______________________________________________________________________________________ 5 electrical characteristics?ual ?v supplies (max4691/max4692/max4693 only) (v+ = +4.5v to +5.5v, v- = -4.5v to -5.5v, v ih = +2v, v il = +0.8v, t a = -40? to +85?, unless otherwise noted.) (notes 3, 4, 5) parameter symbol conditions t a min typ max units analog switch analog signal range v x , v y , v z , v x _, v y _, v z _ - 40c to + 85c v- v+ v + 25c 18 25 on-resistance (note 6) r on v+ = 4.5v; i x , i y , i z = 10ma; v- = -4.5v; v x _, v y _, v z _ = 3.5v - 40c to + 85c 30 + 25c 2 3 on-resistance match between channels (notes 6, 7) r on v+ = 4.5v; v- = -4.5v; i x , i y , i z = 10ma; v x _, v y _, v z _ = 3.5v - 40c to + 85c 4 + 25c 2.5 3.5 on-resistance flatness (note 8) r flat ( on ) v+ = 4.5v; v- = -4.5v; i x , i y , i z = 10ma; v x , v y , v z = 3.5v, 0, -3.5v - 40c to + 85c 4 + 25c -1 1 x_ , y_, z_ off-leakage current (note 9) i x _, i y _, i z _ v+ = 5.5v; v- = -5.5v; v x , v y , v z = + 4.5v; v x _, v y _, v z _ = 4.5v - 40c to + 85c -10 10 na + 25c -2 2 x, y, z off-leakage current (note 9) i x ( off ) , i y(off) , i z(off) v+ = 5.5v; v- = -5.5v; v x , v y , v z = + 4.5v; v x _, v y _, v z _ = 4.5v - 40c to + 85c -20 20 na electrical characteristics?ingle +5v supply (continued) (v+ = +4.5v to +5.5v, v- = 0, v ih = +2v, v il = +0.8v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 3, 4, 5) parameter symbol conditions t a min typ max units off-isolation (note 10) v iso f = 0.1mhz, r l = 50 , c l = 5pf, figure 6 + 25c -80 db crosstalk (note 11) v ct f = 0.1mhz, r l = 50 , c l = 5pf, figure 6 + 25c -87 db digital i/o input logic high v ih 2v input logic low v il 0.8 v input leakage current i in v a , v b , v c , v en = 0 or v+ -1 +1 ? supply + 25c 0.1 positive supply current i+ v+ = 5.5v; v a , v b , v c , v en = 0 or v+ - 40c to + 85c 1 ?
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 6 _______________________________________________________________________________________ note 3: the algebraic convention, where the most negative value is a minimum and the most positive value is a maximum, is used in this data sheet. note 4: ucsp parts are 100% tested at t a = +25?. limits across the full temperature range are guaranteed by correlation. note 5: qfn and tqfn parts are 100% tested at t a = +85?. limits across the full temperature range are guaranteed by correlation. note 6: ucsp r on and r on match are guaranteed by design. note 7: r on = r on(max) - r on(min) . note 8: flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. note 9: leakage parameters are guaranteed by design. note 10: off-isolation = 20log 10 (v w,x,y,z / v w_,x_,y_,z_ ), v w,x,y,z = output, v w_,x_,y_,z_ = input to off switch. note 11: between any two switches. electrical characteristics?ual ?v supplies (continued) (max4691/max4692/max4693 only) (v+ = +4.5v to +5.5v, v- = -4.5v to -5.5v, v ih = +2v, v il = +0.8v, t a = -40? to +85?, unless otherwise noted.) (notes 3, 4, 5) parameter symbol conditions t a min typ max units + 25c -2 2 x, y, z on-leakage current (note 9) i x(on) , i y(on) , i z(on) v+ = 5.5v; v- = -5.5v; v x , v y , v z = 4.5v; v x _, v y _, v z _ = 4.5v, or unconnected - 40c to + 85c -20 20 na dynamic + 25c 55 80 enable turn-on time t on v x _, v y _, v z _ = 3v; r l = 300 , c l = 35pf, figure 2 - 40c to + 85c 90 ns + 25c 35 50 enable turn-off time t off v x _, v y _, v z _ = 3v; r l = 300 , c l = 35pf, figure 2 - 40c to + 85c 60 ns + 25c 60 90 ad d r ess tr ansi ti on ti m et trans v x _, v y _, v z _ = 0, 3v; r l = 300 , c l = 35pf, figure 3 - 40c to + 85c 100 ns + 25c 2 20 break-before-make t bbm v x _, v y _, v z _ = 3v; r l = 300 , c l = 35pf, figure 4 - 40c to + 85c 2 ns charge injection q v gen = 0; r gen = 0; c l = 1nf, figure 5 + 25c 1.8 pc off-isolation (note 10) v iso f = 0.1mhz, r l = 50 , c l = 5pf, figure 6 + 25c -82 db crosstalk (note 11) v ct f = 0.1mhz, r l = 50 , c l = 5pf, figure 7 + 25c -84 db total harmonic distortion thd f = 20hz to 20khz, v x , v y , v z = 5vp-p; r l = 600 , + 25c 0.02 % digital i/o input logic high v ih 2v input logic low v il 0.8 v input leakage current i in v a , v b , v c , v en = 0 or v+ -1 +1 ? supply + 25c 0.1 positive supply current i+ v+ = 5.5v; v- = 5.5v; v a , v b , v c , v en = 0 or v+ - 40c to + 85c 1 ?
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package _______________________________________________________________________________________ 7 40 30 20 10 0 -6 0 -4 -2 2 4 6 on-resistance vs. v x , v y , v z (dual supplies) max4691 toc01 v x , v y , v z (v) r on ( ) v+ = +2.7v v- = -2.7v v+ = +5v v- = -5v v+ = +3.3v v- = -3.3v v+ = +2v v- = -2v 6 10 8 16 14 12 22 20 18 24 -5 -1 -3 135 on-resistance vs. v x , v y , v z and temperature (dual supplies) max4691 toc02 v x , v y , v z (v) r on ( ) v+ = +5v v- = -5v t a = +85 c t a = -40 c t a = +25 c 0 30 20 10 40 50 60 70 80 90 100 04 2681012 on-resistance vs. v w , v x , v y , v z (single supply) max4691 toc03 v w , v x , v y , v z (v) r on ( ) v+ = +2v v+ = +7.5v v+ = +5v v+ = +3.3v v+ = +2.7v v+ = +10v 10 14 12 16 18 20 22 24 26 28 30 32 34 012345 max4691 toc04 on-resistance vs. v w , v x , v y , v z and temperature (single supply) v w , v x , v y , v z (v) r on ( ) v+ = +5v t a = +85 c t a = +25 c t a = -40 c 10 20 30 40 50 00.60.9 0.3 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 max4691 toc05 on-resistance vs. v w , v x , v y , v z and temperature (single supply) v w , v x , v y , v z (v) r on ( ) v+ = +3.3v t a = +85 c t a = +25 c t a = -40 c 10 1 0.1 0.01 0.001 -40 10 -15 356085 supply current vs. temperature (dual supplies) max4691 toc06 temperature ( c) i+, i- (na) v+ = +5v v- = -5v v a , v b , v c , v en = 0, +5v i+ i- 10 1 0.1 0.01 0.001 -40 10 -15 356085 supply current vs. temperature (single supply) max4691 toc07 temperature ( c) i+, i- (na) v+ = +5v v a , v b , v c , v en = 0, +5v 1pa 0.1na 0.01na 1na 0.01 a 0.1 a 1 a 0.01ma 0.1ma 1ma 0.01a 0.1a 1a 012345 i+ vs. logic level max4691 toc08 v a , v b , v c , v enb (v) i+ 0 0.4 0.2 0.8 0.6 1.2 1.0 1.4 1.8 1.6 2.0 2 456 3 7 8 9 10 11 logic-level threshold vs. v+ max4691 toc09 v+ (v) v a , v b , v c , v en (v) typical operating characteristics (t a = +25?, unless otherwise noted.)
frequency response vs. 5v supplies frequency (mhz) 0.001 100 loss (db) max4691 toc16 -140 0 -100 -120 -60 -80 -20 -40 0.01 0.1 1 10 off-isolation crosstalk on-response frequency response vs. +3v supplies frequency (mhz) 0.001 100 loss (db) max4691 toc17 -140 0 -100 -120 -60 -80 -20 -40 0.01 0.1 1 10 off-isolation crosstalk on-response 10 1k 100 10k 100k total harmonic distortion plus noise vs. frequency max4691 toc18 frequency (hz) thd+n (%) 0.1 0.001 0.01 v+ = +5v v- = -5v v+ = +3v v- = 0 max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 8 _______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) 0.0001 0.001 0.1 0.01 1 10 -40 10 -15 35 60 85 on-leakage current vs. temperature max4691 toc10 temperature ( c) on-leakage (na) v+ = +5.5v v- = -5.5v 0.0001 0.001 0.1 0.01 1 10 -40 10 -15 35 60 85 off-leakage current vs. temperature max4691 toc11 temperature ( c) off-leakage (na) v+ = +5.5v v- = -5.5v w, x, y, z w_, x_, y_, z_ 30 40 35 50 45 60 55 65 -40 10 -15 35 60 85 turn-on/turn-off time vs. temperature (dual supply) max4691 toc12 turn-on/turn-off time (ns) temperature ( c) v+ = +5.5v v- = -5.5v turn-on turn-off 30 50 40 70 60 80 90 -40 10 -15 35 60 85 turn-on/turn-off time vs. temperature (single supply) max4691 toc13 turn-on/turn-off time (ns) temperature ( c) v+ = +5.5v turn-on turn-off 30 130 80 230 180 330 280 380 max4691 toc14 supply voltage v+, v- (v) turn-on/turn-off time (ns) 2 3 4 5 6 turn-on/turn-off time vs. supply voltage turn-on turn-off 0 1.0 0.5 2.0 1.5 3.0 2.5 3.5 -5 -1 -3 1 3 -4 0 -2 2 4 5 charge injection vs. v w , v x , v y , v z max4691 toc15 v w , v x , v y , v z (v) q (pc) v+ = +5v v- = -5v v+ = +5v v- = 0 v+ = +3v v- = 0
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package _______________________________________________________________________________________ 9 pin description pin ucsp qfn-ep/ tqfn-ep name function a4, b4, c 4, d 4, a1, b1, c 1, d 1 16, 1, 3, 4, 12, 11, 9, 8 x0?7 analog switch inputs 0? a2 13 x analog switch common d 3, d 2, a3 5, 7, 15 a, b, c digital address inputs b2 14 v- negative analog supply voltage input. connect to gnd for single-supply operation. b3 2 gnd ground. connect to digital ground. (analog signals have no ground reference; they are limited to v+ and v-.) c2 10 en digital enable input. normally connect to gnd. can be driven to logic high to set all switches off. c3 6 v+ positive analog and digital supply voltage input ep exposed pad. connect to v+. max4691 pin ucsp qfn-ep/ tqfn-ep name function a1, b1, c 1, d 1 12, 11, 9, 8 x0?3 analog switch ??inputs 0? a4, b4, c 4, d 4 16, 1, 3, 4 y0?3 analog switch ??inputs 0? a2 13 x analog switch ??common a3 15 y analog switch ??common d 3, d 2 5, 7 a, b digital address inputs for both ??and ??analog switches b2 14 v- negative analog supply voltage input. connect to gnd for single-supply operation. b3 2 gnd ground. connect to digital ground. (analog signals have no ground reference; they are limited to v+ and v-.) c2 10 en digital enable input. normally connect to gnd. can be driven to logic high to set all switches off. c3 6 v+ positive analog and digital supply voltage input ep exposed pad. connect to v+. max4692
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 10 ______________________________________________________________________________________ pin ucsp qfn-ep/ tqfn-ep name function a1 12 x0 analog switch ??normally closed input b1 11 x1 analog switch ??normally open input a4 16 y0 analog switch ??normally closed input b4 1 y1 analog switch ??normally open input d 1 8 z0 analog switch ??normally closed input c1 9 z1 analog switch ??normally open input a2 13 x analog switch ??common a3 15 y analog switch ??common d2 7 z analog switch ??common c4 3 a analog switch ??digital control input d4 4 b analog switch ??digital control input d3 5 c analog switch ??digital control input b2 14 v- negative analog supply voltage input. connect to gnd for single-supply operation. b3 2 gnd ground. connect to digital ground. (analog signals have no ground reference; they are limited to v+ and v-.) c2 10 en digital enable input. normally connect to gnd. can be driven to logic high to set all switches off. c3 6 v+ positive analog and digital supply voltage input ep exposed pad. connect to v+. max4693 pin description (continued)
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package ______________________________________________________________________________________ 11 pin uscp qfn-ep/ tqfn-ep name function d4 4 w0 analog switch ??normally closed input c4 3 w1 analog switch ??normally open input a1 12 x0 analog switch ??normally closed input b1 11 x1 analog switch ??normally open input a4 16 y0 analog switch ??normally closed input b4 1 y1 analog switch ??normally open input d1 8 z0 analog switch ??normally closed input c1 9 z1 analog switch ??normally open input d3 5 w analog switch ??common a2 13 x analog switch ??common a3 15 y analog switch ??common d2 7 z analog switch ??common b2 14 gnd ground b3 2 a analog switch ??and ??digital control input c2 10 b analog switch ??and ??digital control input c3 6 v+ positive analog and digital supply voltage input ep exposed pad. connect to v+. max4694 pin description (continued)
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 12 ______________________________________________________________________________________ detailed description the max4691?ax4694 are low-voltage cmos analog ics configured as an 8-channel multiplexer (max4691), two 4-channel multiplexers (max4692), three spdt switches (max4693), and four spdt switches (max4694). all switches are bidirectional. the max4691/max4692/max4693 operate from either a single +2v to +11v power supply or dual ?v to ?.5v power supplies. when operating from ?v sup- plies they offer 25 on-resistance (r on ), 3.5 max r on flatness, and 3 max matching between channels. the max4694 operates from a single +2v to +11v sup- ply. each switch has rail-to-rail signal handling, fast switching times of t on = 80ns, t off = 50ns, and a low 1na leakage current. all digital inputs are 1.8v logic-compatible when oper- ating from a +3v supply and ttl-compatible when operating from a +5v supply. digital inputs the max4691 and max4692 include address pins that allow control of the multiplexers. for the max4691, pins a, b, c determine which switch is closed. the two 4-1 muxes in the max4692 are controlled by the same address pins (a and b). (table 1) the max4693 and max4694 offer spdt switches in triple and quadruple packages. in the max4693, each switch has a unique control input. the max4694 has two digital control inputs: a (for switches ??and ?? and b (for switches ??and ??. (table 1) applications information power-supply considerations overview the max4691?ax4694 construction is typical of most cmos analog switches. v+ and v-* are used to drive the internal cmos switches and set the limits of the analog voltage on any switch. reverse esd-protection diodes are internally connected between each analog signal pin and both v+ and v-. if any analog signal exceeds v+ or v-, one of these diodes will conduct. * v- is found only on the max4691/max4692/max4693. address bits on switches en 1 c 2 b a max4691 max4692 max4693 max4694 1xxx all switches open all switches open all switches open 0 0 0 0 x-x0 x-x0, y-y0 x-x0, y-y0, z-z0 w-w0, x-x0, y-y0, z-z0 0 0 0 1 x-x1 x-x1, y-y1 x-x1, y-y0, z-z0 w-w1, x-x0, y-y1, z-z0 0 0 1 0 x-x2 x-x2, y-y2 x-x0, y-y1, z-z0 w-w0, x-x1, y-y0, z-z1 0 0 1 1 x-x3 x-x3, y-y3 x-x1, y-y1, z-z0 w-w1, x-x1, y-y1, z-z1 0 1 0 0 x-x4 x-x0, y-y0 x-x0, y-y0, z-z1 w-w0, x-x0, y-y0, z-z0 0 1 0 1 x-x5 x-x1, y-y1 x-x1, y-y0, z-z1 w-w1, x-x0, y-y1, z-z0 0 1 1 0 x-x6 x-x2, y-y2 x-x0, y-y1, z-z1 w-w0, x-x1, y-y0, z-z1 0 1 1 1 x-x7 x-x3, y-y3 x-x1, y-y1, z-z1 w-w1, x-x1, y-y1, z-z1 table 1. truth table/switch programming x = don? care 1. en is not present on the max4694. 2. c is not present on the max4692 and max4694.
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package ______________________________________________________________________________________ 13 during normal operation, these (and other) reverse- biased esd diodes leak, forming the only current drawn from v+ or v-. virtually all the analog leakage current comes from the esd diodes. although the esd diodes on a given signal pin are identical, and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or v- and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and v- pins consti- tutes the analog signal path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage cur- rents of either the same or opposite polarity. v+ and gnd power the internal logic and logic-level translators, and set both the input and output logic lim- its. the logic-level translators convert the logic levels into switched v+ and v- signals to drive the gates of the analog signals. this drive signal is the only connection between the logic supplies (and signals) and the ana- log supplies. v+ and v- have esd-protection diodes on gnd. bipolar supplies the max4691/max4692/max4693 operate with bipolar supplies between ?v and ?.5v. the v+ and v- sup- plies need not be symmetrical, but their difference can- not exceed the absolute maximum rating of +12v. single supply these devices operate from a single supply between +2v and +11v when v- is connected to gnd. all of the bipolar precautions must be observed. at room temperature, they operate with a single supply at near or below +2v, although as supply voltage decreases, switch on-resis- tance and switching times become very high. always bypass supplies with a 0.1? capacitor. overvoltage protection proper power-supply sequencing is recommended for all cmos devices. do not exceed the absolute maxi- mum ratings, because stresses beyond the listed rat- ings can cause permanent damage to the devices. always sequence v+ on first, then v-, followed by the logic inputs and by w, x, y, z. if power-supply sequencing is not possible, add two small signal diodes (d1, d2) in series with the supply pins for over- voltage protection (figure 1). adding diodes reduces the analog signal range to one diode drop below v+ and one diode drop above v-, but does not affect the devices?low switch resistance and low leakage characteristics. device operation is unchanged, and the difference between v+ and v- should not exceed 12v. these protection diodes are not recommended when using a single supply if signal levels must extend to ground. ucsp reliability the chip-scale package (ucsp) represents a unique package that greatly reduces board space compared to other packages. ucsp reliability is integrally linked to the user? assembly methods, circuit board material, and usage environment. the user should closely review these areas when considering a ucsp. performance through operating life test and moisture resistance is equal to conventional package technology as it is primarily deter- mined by the wafer-fabrication process. however, this form factor may not perform equally to a packaged prod- uct through traditional mechanical reliability tests. mechanical stress performance is a greater considera- tion for a ucsp. ucsp solder joint contact integrity must be considered since the package is attached through direct solder contact to the user? pc board. testing done to characterize the ucsp reliability per- formance shows that it is capable of performing reli- ably through environmental stresses. results of environmental stress tests and additional usage data and recommendations are detailed in the ucsp appli- cation note, which can be found on maxim? website, at www.maxim-ic.com. ( ) are for the max4694 only, replace v- with gnd. max4691 max4692 max4693 max4694 com no v- (gnd) v+ *internal protection diodes d2 d1 external blocking diode external blocking diode v- (gnd ) v+ * * * * figure 1. overvoltage protection
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 14 ______________________________________________________________________________________ figure 2. enable transition time 50% t on v+ 0 v x0 v out 0 90% 90% t off 50% t on v+ 0 v x0 , v y0 v out 0 90% 90% t off 50% t on v+ 0 v w0 , v x0 , v y0 , v z0 v out v en v w1 , v x1 , v y1 , v z1 90% 90% t off v out v- gnd b v- a c x0 x1?7 x v+ max4691 300 50 35pf v+ v out v- gnd v+ b v- a x0, y0 x1, x2, x3, y1, y2, y3 x, y v+ max4692 300 50 35pf v+ v out v- gnd v+ v- a b c x1, y1, z1 x0, y0, z0 x, y, z v+ v- max4693 300 35pf 50 v- = 0 for single-supply operation. test each section individually. v en v en v en v en en en v en en v+ v+ test circuits/timing diagrams
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package ______________________________________________________________________________________ 15 figure 3. address transition time 50% t trans v+ 0 v x0 v out v a , v b , v c 0 v x7 90% 90% t trans 50% t trans v+ 0 v x0 , v y0 v out v a , v b 0 v x3 , v y3 90% 90% t trans 50% t trans v+ 0 v w0 , v x0 , v y0 , v z0 v out v a , v b , v c 0 v w1 , v x1 , v y1 , v z1 90% 90% t trans v+ v out v a , v b , v c v a , v b v- gnd v+ b v- a c x0 x1?6 x7 x v+ v- max4691 300 50 35pf v+ v out v- gnd v+ b v- a x0, y0 x1, x2, y1, y2 x3, y3 x, y v+ v- max4692 300 50 35pf v+ v out v- gnd v+ v- a, b, c v a , v b , v c w1, x1, y1, z1 w0, x2, y2, z2, x0, y0, z0 x, y, z v- v+ max4693 max4694 300 50 35pf v- = 0 for single-supply operation. (not present on the max4694) test each section individually. en en en test circuits/timing diagrams (continued)
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 16 ______________________________________________________________________________________ 50% v+ 0 v w , v x , v y , v z v out v a , v b , v c 0 90% t bbm v+ v out v a , v b , v c v a , v b v a , v b , v c v- gnd v+ b v- a c en x0?7 x v+ max4691 300 50 35pf v+ v out v- gnd v+ b v- a x0?3, y0?3 x, y v+ max4692 300 35pf v+ v out v- gnd v+ v- a, b, c w0, w1, x0, x1, y0, y1, z0, z1 w, x, y, z v+ max4693 max4694 300 35pf 50 50 v- = 0 for single-supply operation. (not present on the max4694) test each section individually. t r < 20ns t f < 20ns en en 0 v+ v out is the measured voltage due to charge transfer error q when the channel turns off. v out v- = 0 for single-supply operation. (not present on the max4694) test each section individually. q = v out x c l v out v+ v out v en v- gnd v+ b v- a channel select c w_, x_, y_, z_ w, x, y, z max4691 max4694 50 c l = 1000pf en v en figure 4. break-before-make interval figure 5. charge injection test circuits/timing diagrams (continued)
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package ______________________________________________________________________________________ 17 measurements are standardized against short at socket terminals. off-isolation is measured between com and ?ff?no terminal on each switch. on loss is measured between com and ?n?no terminal on each switch. crosstalk is measured from one channel (a, b, c) to all other channels. signal direction through switch is reversed; worst values are recorded. v- is not present on the max4694. v+ v out v in v- gnd v+ v in v out meas. network analyzer 50 50 50 off-isolation = 20log on-loss = 20log crosstalk = 20log 50 ref. b v- v out v in v out v in a channel select c w_, x_, y_, z_ w, x, y, z 10nf 10nf max4691 max4694 v en en figure 6. off-isolation, on-loss, and crosstalk v+ v- gnd v+ b v- a channel select 1mhz capacitance analyzer c w_, x_, y_, z_ w, x, y, z en max4691 max4694 v- is not present on the max4694. figure 7. capacitance test circuits/timing diagrams (continued)
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 18 ______________________________________________________________________________________ functional diagrams (continued) max4694 w0 w w1 y0 y y1 z0 z z1 x0 x x1 a b max4693 z0 z z1 y0 y y1 x0 ab c x x1 en max4692 x0 x1 x2 x3 x0 x1 x2 x3 logic b a en x y chip information transistor count: 292
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package ______________________________________________________________________________________ 19 top view a b c d 12 3 4 x4 x c x0 x5 v- gnd x1 x1 gnd x2 x3 x6 v+ x2 x7 b a x3 max4691 max4691 1 16 2 3 4 12 11 10 9 x4 x5 en x6 15 14 13 x0 c v- x 5 6 7 8 av+bx7 a b c d 12 3 4 x0 x y y0 x1 v- gnd y1 y1 gnd y2 y3 x2 v+ y2 x3 b a y3 max4692 max4692 1 16 2 3 4 12 11 10 9 x0 x1 en x2 15 14 13 y0 y v- x 5 6 7 8 av+bx3 en en ep* qfn *exposed pad. ucsp tqfn *exposed pad. qfn *exposed pad. ucsp tqfn *exposed pad. ep* max4691 *ep 9 10 11 12 4 3 2 1 x6 en x5 x4 x3 x2 gnd x1 13 14 15 16 8 7 6 5 x v- c x0 x7 b v+ a max4692 *ep 9 10 11 12 4 3 2 1 x2 en x1 x0 y3 y2 gnd y1 13 14 15 16 8 7 6 5 x v- y y0 x3 b v+ a + + pin configurations
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package 20 ______________________________________________________________________________________ pin configurations (continued) a b c d 12 3 4 x0 x y y0 x1 v- gnd y1 y1 gnd a b z1 v+ a z0 z c b max4693 max4693 1 16 2 3 4 12 11 10 9 x0 x1 en z1 15 14 13 y0 y v- x 5 6 7 8 cv+zz0 a b c d 12 3 4 x0 x y y0 x1 gnd a y1 y1 a w1 w0 z1 v+ w1 z0 z w w0 b max4694 max4694 1 16 2 3 4 12 11 10 9 x0 x1 b z1 15 14 13 y0 y gnd x 5 6 7 8 wv+ z z0 en top view ep* ep* qfn *exposed pad. ucsp tqfn *exposed pad. + + qfn *exposed pad. ucsp tqfn *exposed pad. max4693 *ep 9 10 11 12 4 3 2 1 z1 en x1 x0 b a gnd y1 13 14 15 16 8 7 6 5 x v- y y0 z0 z v+ c max4694 *ep 9 10 11 12 4 3 2 1 z1 b x1 x0 w0 w1 a y1 13 14 15 16 8 7 6 5 x gnd y y0 z0 z v+ w package type package code document no. 16-qfn b16-1 21-0101 16-tqfn g1644-1 21-0106 16-ucsp t1644-4 21-0139 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .
max4691?ax4694 low-voltage 8:1 mux/dual 4:1 mux/triple spdt/ quad spdt in ucsp package maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 21 2008 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 4 8/08 adding parts numbers, package diagram, and tqfn packaging 1?6

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